The present invention disclosed herein relates to an analog-to-digital converter, and more particularly, to a successive approximation register analog-to-digital converter and an operation method thereof.
As the use of mixed-mode systems increases, analog-to-digital converters (ADC) become more important. In particular, to reduce the prices of digital video disk players (DVDP) and direct broadcasting for satellite receiver (DRSR) systems, research has been actively conducted on methods of integration into one chip via a CMOS process. One of the most important issues for integration into one chip is how to design an ADC capable of directly processing a radio frequency (RF) signal.
Various types of ADCs have been proposed to date. For instance, a flash ADC, a pipeline ADC, and a successive approximation register (SAR) ADC have been proposed, and are currently used in fields suitable for ADCs. A flash ADC operates at relatively high speed, but consumes a large amount of power. A pipeline ADC operates at high speed and supports high resolution, but occupies a large area. A SAR ADC consumes a small amount of power and has a simple circuit structure, but operates at relatively low speed.